mALUch
About
mALUch is a 16bit custom Instruction Set Architecture with two (work in progress) hardware implementations: one on FPGA and another on 74xx series chips.
History
The project started as a rough idea to develop RV CPU in 2025-05 which was quickly transformed into developing custom 16b ISA to test our (Hubert Wójcik, Łukasz Kmiecik, Mateusz Trzeciak) cooperation and abilities. Initially it was supposed to be project under KN Micro but after discussion we decided to work on it separately and, provided we succeed, we wanted to transform it into new uni club.
For 2 months we have redesigned ISA several times to make it reasonably easy to implement, and around 2025-07 we have gained initial support for creating uni club from FPGA team at AGH. Over the summer break we have finalized the ISA and implemented assembler and simulator.
During 2025-09 we have completed most of the work necessary for kickstarting the uni club, and the project has been effectively transfered there. Then we have divided into 2 groups: one working on FPGA one working on PCB.
Short Technical Overview
mALUch is simple 16bit ISA designed for educational purposes, its instructions are easy to decode and do not require a lot of hardware to execute. At the same time it can support various IOs making it theoretically usable as daily use computer.
ISA
https://github.com/AGH-Logic-Unit/maluch/blob/main/Docs/ISA.md
Software
Software is currently under partial redo.
As of now, there are:
- assembler
- simulator
Simulator is straightforward implementation of ISA in c++, providing simple debugger and interactive window.
Assembler is realized by hijacking c++ compiler which provides powerful metaprogramming capabilities at essentially no development cost.
PCB
PCB is currently under development and possible redo
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│ CONTROL │◄────►│ UNIT │◄────►│ │
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Currently the main implementation done is in the logisim implemented as both:
- behavioral model
- 74xx model Both are fully complete (that is, can simulate full shell), currently we are working on transfering that onto PCB in Kicad.
FPGA
Soft implementation is based on forced one-cycle model. This provides a perfect oportunity to face with real hardware chellenges such as propagation delays.
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│ CLOCK-RESET CONTROL │◄───────┤ PROGRAMMER │
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│ TIMER │◄────┼───►│ IO BRIDGE │◄────►│ CORE │◄─────►│ │◄───►│ MEMORY │
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Currently project entered physical tests phase. Fully developped implementation will be able to:
- run shell
- flash and write to ROM without re-synthezis